The present invention relates, in general, to electronics and, more particularly, to semiconductor device structures and methods of forming semiconductor devices.
Integrated circuits have been classified as analog devices, digital devices, or power devices. Smart Power technologies combine or integrate analog and digital circuits with power devices on or within a single semiconductor substrate. The smart part of the smart power circuit adds, for example, control, diagnostic, and protection functions to the power semiconductor devices. Smart Power technologies have increased the robustness and reliability of power drivers for automotive and industrial applications. Such applications have included, for example, intelligent power switches for controlling an ABS-braking system, system power chips for airbag control, engine management, motor control, switched mode power supplies, intelligent switching of lights, among others.
The integration of logic and analog functions with power transistors on a single semiconductor die presents challenges in the isolation schemes used to physically separate and electrically isolate the different functional devices. Such isolation schemes have included, for example, junction isolation and dielectric isolation schemes. Dielectric isolation schemes have included dielectric trench isolation, which separates components in a lateral direction, but not against the substrate, as well as semiconductor-on-insulator (“SOI”) schemes that provide both lateral isolation and vertical substrate isolation. Another isolation scheme has combined dielectric trench isolation with junction isolation regions that have been disposed adjoining the trench isolation regions within the active regions of the device.
However, the above noted isolation schemes have several shortcomings. For example, junction isolation schemes include doped regions that consume lateral space within the semiconductor chip, which results in larger chips sizes being used to ensure sufficient lateral spacing to sustain breakdown characteristics. Also, because of the larger area taken up by junction isolation schemes, junction isolation schemes also tend to exhibit undesirable high capacitance. SOI technologies provide for reduced chips sizes, but have had issues with thermal dissipation, high on-resistance due to larger average junction temperature, less robustness during inductive clamping, and lower energy capability during an electro-static discharge (“ESD”) event, among others. In addition, in high voltage SOI technology, the parasitic capacitance per unit area of the top layer towards the underlying substrate often exceeds the capacitance per unit area presented by vertical junction isolation. Additionally, SOI technologies are expensive to manufacture.
Accordingly, it is desirable to have an isolation structure and a method of forming the semiconductor devices using the isolation structure that overcomes the shortcomings of prior isolation techniques set forth previously. It is also desirable for the structure and method to support the integration of low voltage and high voltage devices within a single semiconductor chip, to support both a positive bias and a negative bias versus the potential of the bulk substrate in order to increase design flexibility and enhance device performance under adverse operating conditions, to have manageable parasitics, and to have lower manufacturing costs.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current-carrying electrode means an element of a device that carries current through the device, such as a source or a drain of an MOS transistor, an emitter or a collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device, such as a gate of a MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-type regions and certain P-type regions, a person of ordinary skill in the art understands that the conductivity types can be reversed and are also possible in accordance with the present description, taking into account any necessary polarity reversal of voltages, inversion of transistor type and/or current direction, etc. For clarity of the drawings, certain regions of device structures, such as doped regions or dielectric regions, may be illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that, due to the diffusion and activation of dopants or formation of layers, the edges of such regions generally may not be straight lines and that the corners may not be precise angles. Furthermore, the term major surface when used in conjunction with a semiconductor region, wafer, or substrate means the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items. In addition, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including, when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof. It will be understood that, although the terms first, second, etc. may be used herein to describe various members, elements, regions, layers and/or sections, these members, elements, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one member, element, region, layer and/or section from another. Thus, for example, a first member, a first element, a first region, a first layer and/or a first section discussed below could be termed a second member, a second element, a second region, a second layer and/or a second section without departing from the teachings of the present disclosure. It will be appreciated by those skilled in the art that words, during, while, and when as used herein related to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as propagation delay, between the reaction that is initiated by the initial action. Additionally, the term while means a certain action occurs at least within some portion of a duration of the initiating action. The use of word about, approximately or substantially means a value of an element is expected to be close to a state value or position. However, as is well known in the art there are always minor variances preventing values or positions from being exactly stated. Unless specified otherwise, as used herein the word over or on includes orientations, placements, or relations where the specified elements can be in direct or indirect physical contact. Unless specified otherwise, as used herein the word overlapping includes orientations, placements, or relations where the specified elements can at least partly or wholly coincide or align in the same or different planes. It is further understood that the embodiments illustrated and described hereinafter suitably may have embodiments and/or may be practiced in the absence of any element that is not specifically disclosed herein.